1. Technical Field
The present disclosure relates to semiconductor wafers and to wafer dicing processes. More particularly, the present disclosure relates to a method of evaluating a wafer dicing process and to an integrated circuit for evaluating a wafer dicing process.
2. Description of the Related Art
FIG. 1A shows a semiconductor wafer 1 comprising a plurality of integrated circuits 10. Each integrated circuit 10 comprises active and passive electronic components such as transistors, resistors, capacitors . . . , as well as contact pads (not shown). The integrated circuits 10 are separated from each other by scribe lines Si. The scribe lines Si have a width w1 generally on the order of 60-100 μm. After a first testing phase of the integrated circuits 10 on the wafer 1, the integrated circuits 10 are separated from each other in a process known as “wafer dicing” or “wafer singulation” to obtain individual dies. This process comprises cutting the wafer according to the scribe lines Si, for example with a laser or a diamond blade. Once separated, the integrated circuits 10 may then be re-tested and packaged.
FIG. 1B shows an integrated circuit 10 after it has been singulated from the wafer 1 to form a die 11. The die 11 comprises a border 12. Due to the dicing process, the border 12 may present uneven edges, as well as defects such as chips 13 or cracks 14. These defects may propagate into the die 11 and reach the integrated circuit 10, particularly if the die is exposed to environmental factors and mechanical stress, causing a failure of the integrated circuit later.
A visual inspection of the edges of the die 11 is performed either by human operators or by machines using form recognition to verify whether the defects are so significant that the die should be rejected. This type of inspection is time consuming, expensive, and not entirely reliable. Furthermore, not all die 11 are inspected due to their large numbers. As a result, damaged integrated circuits 10 can be delivered to customers and fail at an early stage.
It may therefore be desired to provide a means for electronically detecting chips and cracks in the edges of dice.
U.S. Pat. No. 7,871,832 discloses a method for generating a binary number for identifying an integrated circuit. The method includes arranging conductive lines having different lengths around the periphery of each integrated circuit. When the wafer is diced, some of these conductive lines are cut. The continuity state of each conductive line is then sensed, to generate a binary value, 1 or 0, which is representative of whether the conductive line has been cut or remains uncut. The different binary values are then concatenated and used as a chip identifier number.